Pwr Control Register 4 (Pwr_Cr4) - ST STM32WL55JC Reference Manual

RM0453
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 LPMS[2:0]: Low-power mode selection for CPU2
Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode must be entered
6.6.18 PWR CPU2 control register 3 (PWR_C2CR3)
This register is not reset when exiting Standby modes.
Access: additional APB cycles are needed to access this register versus those needed for a
standard APB access (three for a write and two for a read).
Address offset: 0x084
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
EIWUL Res. Res.
rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 EIWUL: internal wakeup line for CPU2 enable
Bit 14 Reserved, must be kept at reset value.
Bit 13 EWRFIRQ: radio IRQ[2:0] wakeup for CPU2 enable
Bit 12 Reserved, must be kept at reset value.
Bit 11 EWRFBUSY: radio busy wakeup for CPU2 enable
These bits are not reset when exiting Standby mode.
These bits select the low-power mode entered when CPU2 enters the Deep-Sleep mode.
The system low-power mode entered depends also on the PWR_CR1.LPMS[2:0] allowed
Low-power mode from CPU1.
000: Stop 0 mode
001: Stop 1 mode
010: Stop 2 mode
011: Standby mode
1xx: Shutdown mode
instead of Stop 2.
In Standby mode, SRAM2 is preserved, depending on RRS bit configuration in
control register 3 (PWR_CR3).
28 27 26 25
Res. Res. Res.
12 11 10 9
APC Res.
rw rw
0: Internal wakeup line to CPU2 disabled
1: Internal wakeup line to CPU2 enabled
When this bit is set, the radio IRQ[2:0] is enabled and triggers a wakeup from Standby event
to CPU2.
When this bit is set, the radio busy is enabled and triggers a wakeup from Standby event to
CPU2 when a rising or a falling edge occurs. The active edge is configured via the
WRFBUSYP bit in the PWR control register 4
24 23 22
Res. Res. Res.
8 7 6
Res. Res.
rw
(PWR_CR4).
RM0453 Rev 2
Power control (PWR)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res.
rw
PWR
17 16
Res. Res.
1 0
rw rw
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