Figure 34. Procedure State Diagram - ST STM32WL55JC Reference Manual

RM0453
Bits 31:16 KEY[15:0]: Semaphore clear key
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 Reserved, must be kept at reset value.
Bits 11:8 COREID[3:0]: COREID of semaphores to be cleared
Bits 7:0 Reserved, must be kept at reset value.
8.4.8 HSEM interrupt clear register (HSEM_KEYR)
Address offset: 0x144
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
Res. Res. Res. Res.
Bits 31:16 KEY[15:0]: Semaphore clear key
Bits 15:0 Reserved, must be kept at reset value.
This field can be written by software and is always read 0.
If this key value does not match HSEM_KEYR.KEY, semaphores are not affected.
If this key value matches HSEM_KEYR.KEY, all semaphores matching the COREID are
cleared to the free state.
This field can be written by software and is always read 0.
This field indicates the COREID for which the semaphores are cleared when writing the
HSEM_CR.
28 27 26 25
rw rw rw rw
12 11 10 9
Res. Res. Res.
This field can be written and read by software.
Key value to match when clearing semaphores.
24 23 22
KEY[15:0]
rw rw rw
8 7 6
Res. Res. Res.
RM0453 Rev 2
Hardware semaphore (HSEM)
21 20 19 18
rw rw rw rw
5 4 3 2
Res. Res. Res. Res.
17 16
rw rw
1 0
Res. Res.
375/1454
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