ST STM32WL55JC Reference Manual page 436

System configuration controller (SYSCFG)
Bit 2 PVDL: PVD lock enable bit
This bit is set by software and cleared only by a system reset. It can be used to enable and
lock the PVD connection to TIM1/16/17 break input, as well as the PVDE and PLS[2:0] in the
PWR_CR2R register.
0: PVD interrupt disconnected from TIM1/16/17 break input. PVDE and PLS[2:0] bits can be
programmed by the application.
1: PVD interrupt connected to TIM1/16/17 break input. PVDE and PLS[2:0] bits are read only.
Bit 1 SPL: SRAM2 parity lock bit
This bit is set by software and cleared only by a system reset. It can be used to enable and
lock the SRAM2 parity error signal connection to TIM1/16/17 break inputs.
0: SRAM2 parity error signal disconnected from TIM1/16/17 break inputs
1: SRAM2 parity error signal connected to TIM1/16/17 break inputs
Bit 0 CLL: CPU1 LOCKUP (Hardfault) output enable bit
This bit is set by software and cleared only by a system reset. It can be used to enable and
lock the connection of CPU1 LOCKUP (Hardfault) output to TIM1/16/17 break inputs.
0: CPU1 LOCKUP output disconnected from TIM1/16/17 break inputs
1: CPU1 LOCKUP output connected to TIM1/16/17 break inputs
11.2.9 SYSCFG SRAM2 write protection register (SYSCFG_SWPR)
Address offset: 0x020
Reset value: 0x0000 0000
31 30 29
P31WP P30WP P29WP P28WP P27WP P26WP P25WP P24WP P23WP P22WP P21WP P20WP P19WP P18WP P17WP P16WP
rs rs rs
15 14 13
P15WP P14WP P13WP P12WP P11WP P10WP P9WP
rs rs rs
Bit 31 P31WP: SRAM2 1 Kbyte page 31 write protection
These bits are set by software and cleared only by a system reset.
0: Write protection of SRAM2 1 Kbyte page 31 is disabled.
1: Write protection of SRAM2 1 Kbyte page 31 is enabled.
Bit 30 P30WP: SRAM2 1 Kbyte page 30 write protection
Bit 29 P29WP: SRAM2 1 Kbyte page 29 write protection
Bit 28 P28WP: SRAM2 1 Kbyte page 28 write protection
Bit 27 P27WP: SRAM2 1 Kbyte page 27 write protection
Bit 26 P26WP: SRAM2 1 Kbyte page 26 write protection
Bit 25 P25WP: SRAM2 1 Kbyte page 25 write protection
Bit 24 P24WP: SRAM2 1 Kbyte page 24 write protection
Bit 23 P23WP: SRAM2 1 Kbyte page 23 write protection
Bit 22 P22WP: SRAM2 1 Kbyte page 22 write protection
Bit 21 P21WP: SRAM2 1 Kbyte page 21 write protection
Bit 20 P20WP: SRAM2 1K byte page 20 write protection
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28 27 26 25
rs rs rs rs
12 11 10 9
rs rs rs rs
24 23 22
rs rs rs
8 7 6
P8WP P7WP P6WP P5WP
rs rs rs
RM0453 Rev 2
21 20 19 18
rs rs rs rs
5 4 3 2
P4WP P3WP P2WP
rs rs rs rs
RM0453
17 16
rs rs
1 0
P1WP P0WP
rs rs