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General-purpose I/Os (GPIO)
10.4.29
GPIO H bit set/reset register (GPIOH_BSRR)
Address offset: 0x1C18
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Bits 31:20 Reserved, must be kept at reset value.
Bit 19 BR3: Port PH3 reset output data bit [3] in GPIOH_ODR
Note: If both BS3 and BR3 are set, BS3 has priority.
Bits 18:4 Reserved, must be kept at reset value.
Bit 3 BS3: Port PH3 set output data bit [3] in GPIOH_ODR
Bits 2:0 Reserved, must be kept at reset value.
10.4.30
GPIOH configuration lock register (GPIOH_LCKR)
Address offset: 0x1C1C
Reset value: 0x0000 0000
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the lock
sequence has been applied on a port bit, the value of this port bit can no longer be modified
until the next MCU reset or peripheral reset.
Note:
A specific write sequence is used to write to the GPIOH_LCKR register. Only word access
(32-bit long) is allowed during this locking sequence.
Each lock bit freezes a specific configuration register (control and alternate function
registers).
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
420/1454
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
This bit is read clear-write 1. A read to this bit returns the value 0.
0: No action on the corresponding GPIOH_ODR.OD3
1: Resets the corresponding GPIOH_ODR.OD3.
This bit is read clear-write 1. A read to this bit returns the value 0.
0: No action on the corresponding GPIOH_ODR.OD3
1: Sets the corresponding GPIOH_ODR.OD3.
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0453 Rev 2
21
20
19
18
Res.
Res.
BR3
Res.
rc_w1
5
4
3
2
Res.
Res.
BS3
Res.
rc_w1
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
LCK3
Res.
rw
RM0453
17
16
Res.
Res.
1
0
Res.
Res.
17
16
Res.
LCKK
rw
1
0
Res.
Res.
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