ST STM32WL55JC Reference Manual page 895

RM0453
TI1[0]
TIMx_CH1
TI1[1..15]
Internal sources
TIMx_BKIN
Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit
Event
Interrupt & DMA output
1. This signal can be used as trigger for some slave timer, see
(TIM16/TIM17).
Figure 237. TIM16/TIM17 block diagram
Internal clock (CK_INT)
CK_PSC
PSC
prescaler
Input
TI1FP1
IC1
filter &
Prescaler
edge
detector
SBIF
BIF
(2)
Break circuitry
RM0453 Rev 2
General-purpose timers (TIM16/TIM17)
Counter Enable (CEN)
Auto-reload register
U
Stop, clear or up/down
CK_CNT
+/-
CNT counter
C1I
U
IC1PS
Capture/compare 1 register
BRK request
Section 27.3.17: Using timer output as trigger for other timers
REP register
UI
Repetition
U
counter
DTG registers
CC1I
OC1REF
Output
OC1
DTG
control
OC1N
To other
timers for
cross-
(1)
trigerring
TIMx_CH1
TIMx_CH1N
MSv40937V2
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