Documentation Conventions; General Information; List Of Abbreviations For Registers - ST STM32WL55JC Reference Manual

Memory and bus architecture
2 Memory and bus architecture
The following definitions are used in this section:
•
CPU1 = Arm Cortex-M4 with MPU and DSP
•
CPU2 = Arm Cortex-M0+ with MPU
When ESE = 0, CPU2 is non-secure. When ESE = 1, CPU2 is secure.
2.1 System architecture
The main system consists of a 32-bit multilayer AHB bus matrix that interconnects the
following masters and slaves:
•
Six masters:
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• Eight slaves:
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–
–
–
–
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The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously.
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CPU1 core I-bus
CPU1 core D-bus
CPU1 core S-bus
CPU2 core S-bus
DMA1
DMA2
Internal Flash memory on the CPU1 Code bus
Internal Flash memory on CPU1 DCode bus
Internal Flash memory on CPU2 S bus
Internal SRAM1 (32 Kbytes)
Internal SRAM2 (32 Kbytes)
AHB1 peripherals including AHB to APB bridges and APB peripherals (connected
to APB1 and APB2)
AHB2 peripherals
AHB3 peripherals including AHB to APB bridges and APB peripherals (connected
to APB3)
RM0453 Rev 2
RM0453