RM0453
4.10.9
FLASH PCROP zone A start address register
(FLASH_PCROP1ASR)
Address offset: 0x024
Reset value: 0xFFFF FFFF
Default reset value from ST production is given. Subsequently, 0b1111 1111 1111 1111 1111
1111 XXXX XXXX, the option bits are loaded with user values from the Flash memory at
reset release.
Access: no wait state when no Flash memory operation is ongoing. Word, half-word access.
This register can only be written by the CPU1 in RDP level 0 or RDP level 1.
When the system is secure (ESE = 1), this register is further more protected by the
PRIVMODE. When privilege protection is enabled in PRIVMODE, this register provides
write access privilege and can only be written by a privileged access. Unprivileged write
access is ignored and an illegal access event is generated. Unprivileged read access is still
allowed.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PCROP1A_STRT[7:0]: PCROP1A area start offset
4.10.10
FLASH PCROP zone A end address register
(FLASH_PCROP1AER)
Address offset: 0x028
Reset value: 0xFFFF FF00
Default reset value from ST production is given. Subsequently, 0bX111 1111 1111 1111 1111
1111 XXXX XXXX, the option bits are loaded with user values from Flash memory at reset
release.
Access: no wait state when no Flash memory operation is ongoing. Word, half-word access.
PCROP_RDP bit can be accessed with byte access
This register can only be written by the CPU1 in RDP level 0 or RDP level 1.
When the system is secure ESE = 1, this register is further more protected by the
PRIVMODE. When privilege protection is enabled in PRIVMODE, this register provides
write access privilege and can only be written by a privileged access. Unprivileged write
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
PCROP1A_STRT contains the first 1-Kbyte page of the PCROP1A area.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
rw
rw
RM0453 Rev 2
Embedded Flash memory (FLASH)
21
20
19
18
Res.
Res.
Res.
5
4
3
2
PCROP1A_STRT[7:0]
rw
rw
rw
rw
17
16
Res.
Res.
1
0
rw
rw
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