Table of Contents
Advertisement
RM0453
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 SPI2S2EN: CPU2 SPI2S2 clock enable
Bits 13:11 Reserved, must be kept at reset value.
Bit 10 RTCAPBEN: CPU2 RTC APB bus clock enable
Bits 9:1 Reserved, must be kept at reset value.
Bit 0 TIM2EN: CPU2 TIM2 timer clock enable
7.4.37
RCC CPU2 APB1 peripheral clock enable register 2
(RCC_C2APB1ENR2)
Address offset: 0x15C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Note:
When the peripheral clock is not active, the peripheral registers read or write access from
CPU2 is not supported.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 LPTIM3EN: CPU2 low-power timer 3 clocks enable
This bit is set and cleared by software.
0: SPI2S2 clock disabled for CPU2
1: SPI2S2 clock enabled for CPU2
This bit is set and cleared by software. RTC kernel clock is controlled by the RTCEN bit in
the RCC_BDCR register.
0: RTC APB bus clock disabled for CPU2
1: RTC APB bus clock enabled for CPU2
This bit is set and cleared by software.
0: TIM2 clock disabled for CPU2
1: TIM2 clock enabled for CPU2
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
This bit is set and cleared by software.
0: LPTIM3 bus and kernel clocks disabled for CPU2
1: LPTIM3 bus and kernel clocks enabled for CPU2
24
23
22
Res.
Res.
Res.
8
7
6
LPTIM3
LPTIM2
Res.
Res.
EN
rw
RM0453 Rev 2
Reset and clock control (RCC)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
EN
rw
17
16
Res.
Res.
1
0
LP
Res.
UART1
EN
rw
345/1454
363
Advertisement
Chapters
Table of Contents
Need help?
Do you have a question about the STM32WL55JC and is the answer not in the manual?
Questions and answers