Table 90. Cpu2 Vector Table - ST STM32WL55JC Reference Manual

Nested vectored interrupt controller (NVIC)
Type of
priority
28 31 Settable
29 32 Settable
30 33 Settable SUBGHZSPI
31 34 Settable
1. C2IMRx[n] refer to the pre-mask bit[n] in SYSCFG_C2IMRx register.
2. EXTI[n] refer to the input event number [n] of the EXTI.
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Table 90. CPU2 vector table (continued)
Acronym
USART2 USART2 global interrupt
LPUART1 LPUART1 global interrupt
Sub-GHz radio SPI global interrupt
Radio IRQ Radio IRQs
Busy RFBUSY interrupt through EXTI[45]
(1)(2)
Description
RM0453 Rev 2
RM0453
Address
0x0000 00B0
0x0000 00B4
0x0000 00B8
0x0000 00BC