Sub-Ghz Radio Generic Cfo Lsb Register (Subghz_Gcforl); Sub-Ghz Radio Generic Packet Control 1 Register; (Subghz_Gpktctl1R); Sub-Ghz Radio Generic Packet Control 1A Register - ST STM32WL55JC Reference Manual

RM0453
Bits 7:0 SYNCWORD[15:8]: Second byte of generic packet synchronization word
5.10.15 Sub-GHz radio generic synchronization word control register 0
(SUBGHZ_GSYNCR0)
Address offset: 0x06C7
Reset value: 0x64
7 6
rw rw
Bits 7:0 SYNCWORD[7:0]: First byte of generic packet synchronization word
5.10.16 Sub-GHz radio LoRa synchronization word MSB register
(SUBGHZ_LSYNCRH)
Address offset: 0x0740
Reset value: 0x14
7 6
rw rw
Bits 7:0 SYNCWORD[15:8]: LoRa synchronization word MSB bits [15:8]
5.10.17 Sub-GHz radio LoRa synchronization word LSB register
(SUBGHZ_LSYNCRL)
Address offset: 0x0741
Reset value: 0x24
7 6
rw rw
Bits 7:0 SYNCWORD[7:0]: LoRa synchronization word LSB bits [7:0]
5
rw
5
rw
0x14: LoRa private network
0x34: LoRa public network
Others: reserved
5
rw
0x24: LoRa private network
0x44: LoRa public network
Others: reserved
4 3
SYNCWORD[7:0]
rw rw
4 3
SYNCWORD[15:8]
rw rw
4 3
SYNCWORD[7:0]
rw rw
RM0453 Rev 2
Sub-GHz radio (SUBGHZ)
2 1
rw rw
2 1
rw rw
2 1
rw rw
0
rw
0
rw
0
rw
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