ST STM32WL55JC Reference Manual page 582

Analog-to-digital converter (ADC)
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog.
Refer to
ADC_AWDxTR) on page
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 LT1[11:0]: Analog watchdog 1 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Refer to
ADC_AWDxTR) on page
18.12.8 ADC watchdog threshold register (ADC_AWD2TR)
Address offset: 0x24
Reset value: 0x0FFF 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 HT2[11:0]: Analog watchdog 2 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog.
Refer to
ADC_AWDxTR) on page
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 LT2[11:0]: Analog watchdog 2 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Refer to
ADC_AWDxTR) on page
582/1454
Section 18.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR,
557.
Section 18.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR,
557.
28 27 26 25
rw rw rw
12 11 10 9
rw rw rw
Section 18.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR,
557.
Section 18.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR,
557.
24 23 22
HT2[11:0]
rw rw rw
8 7 6
LT2[11:0]
rw rw rw
RM0453 Rev 2
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
RM0453
17 16
rw rw
1 0
rw rw