Table 79. Programmable Data Width And Endian Behavior (When Pinc = Minc = 1) - ST STM32WL55JC Reference Manual

RM0453
13.5 DMA interrupts
An interrupt can be generated on a half transfer, transfer complete or transfer error for each
DMA channel x (whatever the channel is secure or non-secure). Separate interrupt enable
bits are available for flexibility.
Interrupt request
Half transfer on channel x
Transfer complete on channel x
Channel x interrupt
Transfer error on channel x
Half transfer or transfer complete or transfer error on channel x
13.6 DMA registers
Refer to
The DMA registers have to be accessed by words (32-bit).
13.6.1 DMA interrupt status register (DMA_ISR)
Address offset: 0x00
Reset value: 0x0000 0000
This register may mix secure and non secure information, depending on the secure mode of
each channel (SECM bit of the DMA_CCRx register). A secure software can read the full
interrupt status. A non-secure software is restricted to read the status of non-secure
channel(s), other secure bit fields returning zero.
This register may mix privileged and unprivileged information, depending on the privileged
mode of each channel (PRIV bit of the DMA_CCRx register). A privileged software can read
the full interrupt status. An unprivileged software is restricted to read the status of
unprivileged channel(s), other privileged bit fields returning zero.
Every status / flag bit is set by hardware, independently of the privileged and the secure
mode of the channel.
Every status bit is cleared by hardware when the software sets the corresponding clear bit
or the corresponding global clear bit CGIFx, in the DMA_IFCR register, provided that, if the
channel x is in privileged mode and/or in secure mode, then the software access to
DMA_IFCR is also privileged and/or secure.
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
TEIF4 HTIF4 TCIF4 GIF4
r r r
Table 80. DMA interrupt requests
Interrupt event
Section 1.2 for a list of abbreviations used in register descriptions.
27 26 25
TEIF7 HTIF7 TCIF7
r r r
11 10 9
TEIF3 HTIF3 TCIF3
r r r r
Direct memory access controller (DMA)
24 23 22
GIF7 TEIF6 HTIF6 TCIF6
r r r
8 7 6
GIF3 TEIF2 HTIF2 TCIF2
r r r
RM0453 Rev 2
Event flag
HTIFx
TCIFx
TEIFx
GIFx
21 20 19 18
GIF6 TEIF5 HTIF5
r r r r
5 4 3 2
GIF2 TEIF1 HTIF1
r r r r
Interrupt
enable bit
HTIEx
TCIEx
TEIEx
-
17 16
TCIF5 GIF5
r r
1 0
TCIF1 GIF1
r r
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