Gtzc Functional Description; Gtzc Block Diagram; Figure 4. Gtzc Security Architecture - ST STM32WL55JC Reference Manual

Global security controller (GTZC)
Note: Some registers have only write security protection and can be accessed read non-secure
(refer to individual register descriptions).
•
Illegal unprivileged read write access
Any unprivileged transaction trying to access a privileged resource is considered as
illegal. In all cases, the addressed resource generates an illegal access event for illegal
read /write access.
Note: Some registers have only write privileged protection and can be accessed read unprivileged
(refer to individual register descriptions).
•
Illegal secure memory fetch access
Any secure memory fetch access transaction trying to access a non-secure memory
resource is considered as illegal. The addressed resource generates an illegal access
event and a bus error.
• Illegal non-secure memory fetch access
Any non-secure memory fetch access transaction trying to access a secure memory
resource is considered as illegal. The addressed resource generates an illegal access
event and a bus error.
•
Illegal unprivileged memory fetch access
Any unprivileged memory fetch access transaction trying to access a privileged
memory resource is considered as illegal. The addressed resource generates an illegal
access event and a bus error.
•
Peripheral fetch access
Any peripheral fetch access is considered as illegal. The bus bridge generates a bus
error for all peripheral fetch access (no illegal access event).
Note: Secure read/write transactions to non-secure memory and peripheral are granted and legal.
Privileged read/write transactions to unprivileged memory and peripheral are granted and
legal.
Privileged fetch transactions to unprivileged memory are granted and legal.
80/1454 RM0453 Rev 2
RM0453