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RM0453
Bit 14 SPI2S2EN: CPU1 SPI2S2 clock enable
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGEN: CPU1 Window watchdog clock enable
Bit 10 RTCAPBEN: CPU1 RTC APB bus clock enable
Bits 9:1 Reserved, must be kept at reset value.
Bit 0 TIM2EN: CPU1 timer 2 clock enable
7.4.19
RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2)
Address offset: 0x05C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Note:
When the peripheral clock is not active, the peripheral registers read or write access from
CPU1 is not supported.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
This bit is set and cleared by software.
0: SPI2S2 clock disabled for CPU1
1: SPI2S2 clock enabled for CPU1
This bit is set by software to enable the window watchdog clock. It is reset by hardware
system reset. This bit is forced to 1 by hardware when the hardware WWDG_SW option is
reset.
0: Window watchdog clock disabled for CPU1
1: Window watchdog clock enabled for CPU1
This bit is set and cleared by software.
RTC kernel clock is controlled by RCC_BDCR register bit RTCEN bit.
0: RTC APB bus clock disabled for CPU1
1: RTC APB bus clock enabled for CPU1
This bit is set and cleared by software.
0: TIM2 clock disabled for CPU1
1: TIM2 clock enabled for CPU1
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
rw
RM0453 Rev 2
Reset and clock control (RCC)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
rw
17
16
Res.
Res.
1
0
Res.
rw
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