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RM0453
30.4.2
IWDG prescaler register (IWDG_PR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:3 Reserved, must be kept at reset value.
Bits 2:0 PR[2:0]: Prescaler divider
Note: Reading this register returns the prescaler value from the V
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
These bits are write access protected see
are written by software to select the prescaler divider feeding the counter clock. PVU bit of
the
IWDG status register (IWDG_SR)
prescaler divider.
000: divider /4
001: divider /8
010: divider /16
011: divider /32
100: divider /64
101: divider /128
110: divider /256
111: divider /256
value may not be up to date/valid if a write operation to this register is ongoing. For this
reason the value read from this register is valid only when the PVU bit in the
status register (IWDG_SR)
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
Section 30.3.5: Register access
must be reset in order to be able to change the
is reset.
RM0453 Rev 2
Independent watchdog (IWDG)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
rw
voltage domain. This
DD
17
16
Res.
Res.
1
0
PR[2:0]
rw
rw
protection. They
IWDG
979/1454
983
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