Sub-Ghz Radio Smps Control 0 Register (Subghz_Smpsc0R); Sub-Ghz Radio Power Control Register (Subghz_Pcr); Sub-Ghz Radio Smps Control 2 Register (Subghz_Smpsc2R) - ST STM32WL55JC Reference Manual

RM0453
1. The reset temporization t
6.2.2 Programmable voltage detector (PVD)
The PVD can be used to monitor V
PLS[2:0] bits in the
PVD can also be used to monitor a voltage level on the PVD_IN pin. In this case the voltage
level on PVD_IN is compared to the internal VREFINT level.
PVD is enabled by setting the PVDE bit.
A PVDO flag is available in the
voltage level on PVD_IN is higher or lower than the PVD threshold. This event is internally
connected to the EXTI line 16 and can generate an interrupt if enabled through the EXTI
registers.
The PVD output interrupt can be generated when V
below the PVD threshold and/or when V
threshold depending on EXTI line 16 rising/falling edge configuration. As an example, the
service routine can perform emergency shutdown tasks.
The PVD can be configured to monitor the V
operation. For this, the PVD must select its lowest level and PVD and the wakeup must be
enabled in EWPVD. Only a voltage drop below the PVD level generates a wakeup event.
BOR0 level cannot be disabled. The other BOR levels can be enabled by user option. When
enabled, BOR is active in all power modes except in Shutdown.
Figure 20. Brownout reset waveform
V
DD
BORH
rise
nPwr
RSTTEMPO
PWR control register 2
Power status register 2 (PWR_SR2)
hysteresis
is present only for the BOR lowest threshold (V
by comparing it to a threshold selected by the
DD
(PWR_CR2).
DD
or voltage level on PVD_IN rises above the PVD
DD
supply level needed for the sub-GHz radio
DD
RM0453 Rev 2
Power control (PWR)
BORH
).
BOR0
to indicate if V
or voltage level on PVD_IN drops
fall
t
MS44480V1
or the
DD
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