ST STM32WL55JC Reference Manual page 136

Embedded Flash memory (FLASH)
Bits 23:21 Reserved, must be kept at reset value.
Bit 20 SYSF_ECC: system Flash memory ECC fail
Bits 19:17 Reserved, must be kept at reset value.
Bits 16:0 ADDR_ECC[16:0]: ECC fail double-word address
4.10.8 FLASH option register (FLASH_OPTR)
Address offset: 0x020
Reset value: 0x3FFF F0AA
Default reset value from ST production is given. Subsequently, 0bXX11 XXXX X111 XXXX
1XXX XXXX XXXX XXXX, the option bits are loaded with user values from the Flash
memory at reset release.
Access: no wait state when no Flash memory operation is ongoing. Word, half-word and
byte access.
This register can only be written by the CPU1 in RDP level 0 or RDP level 1.
When the system is secure (ESE = 1), this register is further more protected by the
PRIVMODE. When privilege protection is enabled in PRIVMODE, this register provides
write access privilege and can only be written by a privileged access. Unprivileged write
access is ignored and an illegal access event is generated. Unprivileged read access is still
allowed.
31 30 29
BOOT_
Res. Res.
LOCK
rw rw
15 14 13
nRST_ nRST_ nRST_
Res.
SHDW STDBY STOP
rw rw
136/1454
This bit indicates that the ECC error correction or double ECC error detection is located in
the system Flash memory.
This bit indicates that double-word address is concerned by the ECC error correction or
causes the double ECC error detection.
28 27 26 25
rw rw rw
12 11 10 9
BOR_LEV[2:0]
rw rw rw rw
24 23 22
Res.
rw rw
8 7 6
ESE
rw rw rw
RM0453 Rev 2
21 20 19 18
WWDG IWDG_
Res. Res.
_SW STDBY
rw rw
5 4 3 2
RDP[7:0]
rw rw rw rw
RM0453
17 16
IWDG_ IWDG_
STOP SW
rw rw
1 0
rw rw