Figure 228. Control Circuit In Gated Mode - ST STM32WL55JC Reference Manual

RM0453
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.
Counter clock = CK_CNT = CK_PSC
26.3.19 Timer synchronization
The TIMx timers are linked together internally for timer synchronization or chaining. When
one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of
another Timer configured in Slave Mode.
Figure 231: Master/Slave timer example
with 1 channel only timers
selection blocks.
Clock
Prescaler
Figure 230. Control circuit in external clock mode 2 + trigger mode
TI1
CEN/CNT_EN
ETR
Counter register
TIF
present an overview of the trigger selection and the master mode
Figure 231. Master/Slave timer example
TIM1
MMS
UEV
Master
TRGO1
mode
control
Counter
34
and Figure 232: Master/slave connection example
TS
SMS
Slave
ITR1
mode
control
Input
trigger
selection
RM0453 Rev 2
General-purpose timer (TIM2)
35
TIM2
CK_PSC
Prescaler
36
MS33110V1
Counter
MS32694V1
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