Sub-Ghz Radio Rtc Period Msb Register (Subghz_Rtcprdr2); Sub-Ghz Radio Rtc Period Mid-Byte Register; (Subghz_Rtcprdr1); Sub-Ghz Radio Rtc Period Lsb Register (Subghz_Rtcprdr0) - ST STM32WL55JC Reference Manual

RM0453
The battery charging is enabled by setting VBE bit in the
(PWR_CR4), and automatically disabled in VBAT mode.
6.1.3 Voltage regulator
Two embedded linear voltage regulators supply all the digital circuitries, except for the
Standby circuitry and the Backup domain. The main regulator (MR) output voltage (V
can be programmed by software to two different power ranges (range 1 and range 2) to
optimize the consumption depending on the system maximum operating frequency (refer to
Section 7.2.9: Clock source frequency versus voltage scaling
access latency.
The voltage regulators are always enabled after a reset. Depending on the application
modes, the V
regulator (LPR), as detailed below:
•
In Run, Sleep and Stop 0 modes, both regulators are enabled and the main regulator
(MR) supplies full power to the V
•
In LPRun and LPSleep modes, the main regulator (MR) is off and the low-power
regulator (LPR) supplies reduced power to the V
of the registers and internal SRAM1 and SRAM2.
•
In Stop 1 and Stop 2 modes, the main regulator (MR) is off and the low-power regulator
(LPR) supplies low power to the all or part of the V
contents of all or part of the registers and of internal SRAM1 and SRAM2.
•
In Standby modes with SRAM2 content preserved (RRS bit set in the
register 3
(LPR) provides the supply to SRAM2 only. The core and digital peripherals (except
Standby circuitry and Backup domain), SRAM1 is powered off.
•
In Standby mode, both regulators (MR and LPR) are powered off. The contents of the
registers and of SRAM1 and SRAM2 is lost except for the Standby circuitry and the
Backup domain.
•
In Shutdown mode, both regulators are powered off. When exiting from Shutdown
mode, a power-on reset is generated. Consequently, the contents of the registers and
of both SRAM1 and SRAM2 is lost, except for the Backup domain.
6.1.4 Dynamic voltage scaling management
The dynamic voltage scaling is a power management technique that consists in increasing
or decreasing the voltage used for the digital peripherals (V
application performance and power consumption needs.
Dynamic voltage scaling to increase V
the device performance.
Dynamic voltage scaling to decrease V
power, particularly in laptop and other mobile devices where the energy comes from a
battery and is thus limited.
•
range 1: high-performance range
The main regulator provides a typical output voltage at 1.2 V. The system clock
frequency can be up to 64 MHz. The Flash memory access time for read access is
supply is provided either by the main regulator or by the low-power
CORE
(PWR_CR3)), the main regulator (MR) is off and the low-power regulator
RM0453 Rev 2
PWR control register 4
domain (core, memories and digital peripherals).
CORE
domain, preserving the contents
CORE
CORE
is known as "overvolting". It is used to improve
CORE
is known as "undervolting". It is used to save
CORE
Power control (PWR)
and to Section 4.3.4: Read
domain, preserving the
PWR control
), according to the
CORE
)
CORE
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