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Extended interrupts and event controller (EXTI)
16.6.7
EXTI software interrupt event register (EXTI_SWIER2)
Address offset: 0x028
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
SWI45
Res.
rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 SWI45: software interrupt on event 45
Bits 12:10 Reserved, must be kept at reset value.
Bit 9 SWI41: software interrupt on event 41
Bit 8 SWI40: software interrupt on event 40
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 SWI34: software interrupt on event 34
Bits 1:0 Reserved, must be kept at reset value.
16.6.8
EXTI pending register (EXTI_PR2)
Address offset: 0x02C
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
PIF45
Res.
rw
518/1454
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
SWI41
rw
A software interrupt is generated independently from the setting in EXTI_RTSR and
EXTI_FTSR. This bit always returns 0 when read.
0: Writing 0 has no effect.
1: Writing 1 to this bit triggers an event on line 45.
This bit is automatically cleared by hardware.
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
PIF41
rw
24
23
22
Res.
Res.
Res.
Res.
8
7
6
SWI40
Res.
Res.
Res.
rw
24
23
22
Res.
Res.
Res.
Res.
8
7
6
PIF40
Res.
Res.
Res.
rw
RM0453 Rev 2
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
Res.
SWI34
rw
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
Res.
PIF34
rw
RM0453
17
16
Res.
Res.
1
0
Res.
Res.
17
16
Res.
Res.
1
0
Res.
Res.
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