ST STM32WL55JC Reference Manual page 344

Reset and clock control (RCC)
7.4.36 RCC CPU2 APB1 peripheral clock enable register 1
(RCC_C2APB1ENR1)
Address offset: 0x158
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access from
CPU2 is not supported.
31 30 29 28
LPTIM1 DAC
Res. Res.
EN EN
rw rw
15 14 13 12
SPI2S2
Res. Res. Res.
EN
rw
Bit 31 LPTIM1EN: CPU2 low-power timer 1 clocks enable
Bit 30 Reserved, must be kept at reset value.
Bit 29 DACEN: CPU2 DAC clock enable
Bits 28:24 Reserved, must be kept at reset value.
Bit 23 I2C3EN: CPU2 I2C3 clocks enable
Bit 22 I2C2EN: CPU2 I2C2 clocks enable
Bit 21 I2C1EN: CPU2 I2C1 clocks enable
Bits 20:18 Reserved, must be kept at reset value.
Bit 17 USART2EN: CPU2 USART2 clock enable
344/1454
27 26 25
Res. Res. Res.
11 10 9
RTC
Res. APB Res.
EN
rw
This bit is set and cleared by software.
0: LPTIM1 bus and kernel clocks disabled for CPU2
1: LPTIM1 bus and kernel clocks enabled for CPU2
This bit is set and cleared by software.
0: DAC clock disabled for CPU2
1: DAC clock enabled for CPU2
This bit is set and cleared by software.
0: I2C3 bus and kernel clocks disabled for CPU2
1: I2C3 bus and kernel clocks enabled for CPU2
This bit is set and cleared by software.
0: I2C2 bus and kernel clocks disabled for CPU2
1: I2C2 bus and kernel clocks enabled for CPU2
This bit is set and cleared by software.
0: I2C1 bus and kernel clocks disabled for CPU2
1: I2C1 bus and kernel clocks enabled for CPU2
This bit is set and cleared by software.
0: USART2 bus and kernel clocks disabled for CPU2
1: USART2 bus and kernel clocks enabled for CPU2
24 23 22 21
I2C3 I2C2 I2C1
Res.
EN EN EN
rw rw rw
8 7 6 5
Res. Res. Res. Res.
RM0453 Rev 2
20 19 18
USART2
Res. Res. Res.
4 3 2
Res. Res. Res.
RM0453
17 16
Res.
EN
rw
1 0
TIM2
Res.
EN
rw