Table 120. Vref Buffer Modes - ST STM32WL55JC Reference Manual

RM0453
20.3 VREFBUF registers
20.3.1 VREFBUF control and status register (VREFBUF_CSR)
Address offset: 0x00
Reset value: 0x0000 0002
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 VRR: Voltage reference buffer ready
Bit 2 VRS: Voltage reference scale
This bit selects the value generated by the voltage reference buffer.
Bit 1 HIZ: High impedance mode
Bit 0 ENVR: Voltage reference buffer mode enable
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
0: the voltage reference buffer output is not ready.
1: the voltage reference buffer output reached the requested level.
0: Voltage reference set to V
1: Voltage reference set to V
This bit controls the analog switch to connect or not the V
0: V pin is internally connected to the voltage reference buffer output.
REF+
1: V pin is high impedance.
REF+
Refer to Table 120: VREF buffer modes
configuration.
This bit is used to enable the voltage reference buffer mode.
0: Internal voltage reference mode disable (external voltage reference mode).
1: Internal voltage reference mode (reference buffer enable or hold mode) enable.
Voltage reference buffer (VREFBUF)
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
(around 2.048 V).
REF_OUT1
(around 2.5 V).
REF_OUT2
for the mode descriptions depending on ENVR bit
RM0453 Rev 2
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. VRR VRS
r rw
pin.
REF+
17 16
Res. Res.
1 0
HIZ ENVR
rw rw
619/1454
620