Sub-Ghz Radio Random Number Register 3 (Subghz_Rngr3); Sub-Ghz Radio Random Number Register 2 (Subghz_Rngr2); Sub-Ghz Radio Random Number Register 1 (Subghz_Rngr1) - ST STM32WL55JC Reference Manual

RM0453
VREF+ pin is not available on all packages. When not available, this pin is internally
bonded to VDDA. When VREF+ is double-bonded with VDDA in a package, the
internal voltage reference buffer is not available and must be kept disabled (refer to the
datasheet for pinout descriptions).
During power up and power down, the following power sequence is required:
1. When V
During power down, V
energy provided to the device remains below 1 mJ. This allows external decoupling
capacitors to be discharged with different time constants during this transient phase.
2. When V
An embedded linear voltage regulator is used to supply the internal digital power V
V is the power supply for digital peripherals, SRAM1 and SRAM2. The Flash memory
CORE
is supplied by V
part V
DDI
LPR
< 1 V other power supplies (V
DD
can temporarily become lower then other supplies only if the
DD
> 1 V, all other power supplies (V
DD
and V . V
CORE DD
.
Figure 18. Power supply overview
V
LP
V
BKP
V
DDO
) must remain below V
DDA
) become independent.
DDA
is split in two parts: V
CORE
V
SW
en
POR
LDO/SMPS
FW mode
mode
MR
V
MAIN
V
DDI
RM0453 Rev 2
Power control (PWR)
+ 300 mV.
DD
part and an interruptible
DDO
V
BAT
V
DD
V
DDSMPS
V
LXSMPS
V
FBSMPS
V
DDRF1V5
RFLDO
V
RF
.
CORE
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