ST STM32WL55JC Reference Manual page 332

Reset and clock control (RCC)
7.4.29 RCC peripherals independent clock configuration register
(RCC_CCIPR)
Address offset: 0x088
Reset value: 0x0000 0000
Access: no wait states, word, half-word and byte access
31 30 29
RNGSEL[1:0] ADCSEL[1:0]
rw rw rw
15 14 13
I2C2SEL[1:0] I2C1SEL[1:0]
rw rw rw
Bits 31:30 RNGSEL[1:0]: RNG clock source selection
Bits 29:28 ADCSEL[1:0]: ADC clock source selection
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:22 LPTIM3SEL[1:0]: Low-power timer 3 clock source selection
Bits 21:20 LPTIM2SEL[1:0]: Low-power timer 2 clock source selection
Bits 19:18 LPTIM1SEL[1:0]: Low-power timer 1 clock source selection
332/1454
28 27 26 25
Res. Res. Res.
rw
12 11 10 9
LPUART1SEL SPI2S2SEL
[1:0]
rw rw rw rw
These bits are set and cleared by software to select the clock source used by the true RNG.
00: PLL "Q" clock (PLLQCLK) selected
01: LSI clock selected
10: LSE clock selected
11: MSI clock selected
These bits are set and cleared by software to select the clock source used by the ADC
interface.
00: No clock selected
01: HSI16 clock selected
10: PLL "P" clock (PLLPCLK) selected
11: System clock (SYSCLK) selected
These bits are set and cleared by software to select the LPTIM3 clock source.
00: PCLK selected
01: LSI clock selected
10: HSI16 clock selected
11: LSE clock selected
These bits are set and cleared by software to select the LPTIM2 clock source.
00: PCLK selected
01: LSI clock selected
10: HSI16 clock selected
11: LSE clock selected
These bits are set and cleared by software to select the LPTIM1 clock source.
00: PCLK selected
01: LSI clock selected
10: HSI16 clock selected
11: LSE clock selected
24 23 22
Res. LPTIM3SEL[1:0] LPTIM2SEL[1:0] LPTIM1SEL[1:0]
rw rw
8 7 6
Res. Res.
[1:0]
rw
RM0453 Rev 2
21 20 19 18
rw rw rw rw
5 4 3 2
USART2SEL
Res. Res.
[1:0]
rw rw
RM0453
17 16
I2C3SEL[1:0]
rw rw
1 0
USART1SEL
[1:0]
rw rw