ST STM32WL55JC Reference Manual page 380

Inter-processor communication controller (IPCC)
Processor
SEND A = 1
RECEIVE B = 2
SEND A = 2
RECEIVE B = 1
Once the sending processor has posted the communication data in the memory, it sets the
channel status flag CHnF to occupied with CHnS.
Once the receiving processor has retrieved the communication data from the memory, it
clears the channel status flag CHnF back to free with CHnC.
TX free interrupt
RX occupied interrupt
Memory occupation
380/1454
Table 68. Bits used for the communication
IPCC_C1CR.TXFIE
IPCC_C1MR.CHnFM
IPCC_C1SCR.CHnS
IPCC_C1TOC2SR.CHnF
IPCC_C2CR.TXFIE
IPCC_C2MR.CHnFM
IPCC_C2SCR.CHnS
IPCC_C2TOC1SR.CHnF
Figure 37. IPCC Simplex channel mode transfer timing
Write
communication
data
Processor A
CHnF
Processor B
A
Read
communication
data
Communication data
RM0453 Rev 2
B
IPCC_C2CR.RXOIE
IPCC_C2MR.CHnOM
IPCC_C2SCR.CHnC
IPCC_C1CR.RXOIE
IPCC_C1MR.CHnOM
IPCC_C1SCR.CHnC
Write
communication
data
Communication data
RM0453
MS42430V1