Pwr Extended Status And Status Clear Register (Pwr_Extscr) - ST STM32WL55JC Reference Manual

RM0453
LSIPRE
LSI RCC 32 kHz
/1,128
LSCO
LSE OSC
OSC32_OUT
32.768 kHz
OSC32_IN
LSE CSS
MCO
/1 - 16
HSE32 OSC
OSC_OUT
32 MHz
OSC_IN
HSE CSS
HSI16 RC
16 MHz
MSI RC
100 kHz - 48 MHz
MSI
HSI16
/M
PLL
xN /P
/Q
/R
1. For full details about the internal and external clock source characteristics, refer to the electrical characteristics section in
the device datasheet.
2. The ADC clock can additionally be derived from the AHB clock of the ADC bus interface, divided by a programmable factor
(1, 2 or 4). When the programmable factor is 1, the AHB prescaler must be equal to 1.
7.2.1 HSE32 clock with trimming
The HSE32 32 MHz external oscillator has the advantage of producing a very accurate rate
on the main clock. The HSE32 furthermore provides on-chip trimming capability.
The high-speed external clock signal (HSE32) can be generated from the following clock
sources:
•
HSE32 external crystal
•
HSE32 external clock
–
–
The clock source must be placed as close as possible to the oscillator pins in order to
minimize output distortion and startup stabilization time.
Figure 27. Clock tree
LSI
/32
LSE
HSE32
SYSCLK
PLLRCLK
PLLQCLK
PLLPCLK
HSI16
PLLRCLK
MSI
HSEPRE
HSE32
/1,2
HSI16
HSI16
SYSCLK
PLLPCLK
PLLQCLK
HSI16
PLLRCLK
I2S_CKIN
external clock source
external TCXO
LSI
LSE
CPU1
HPRE
/1,2,...,512
SYS clock
source
control
MSI
SYSCLK
CPU2
C2HPRE
1,2,...,512
AHB3
SHDHPRE
/1,2,...,512
PCLKn
SYSCLK
to ADC
LSI
to SPI2S2 LSE to RNG
MSI
LSI
RM0453 Rev 2
Reset and clock control (RCC)
HCLK1
/8
APB1
PCLK1
PPRE1
/1,2,4,8,16
APB2
PCLK2
PPRE2
/1,2,4,8,16
HCLK2
/8
HCLK3 to AHB3, Flash, SRAM1, SRAM2
PCLK3
PCLKn
HSI16
to USART1
HSI16 to USART2
to LPUART1
LSE
PCLKn
SYSCLK to I2C1
to I2C2
HSI16 to I2C3
DAC
to IWDG
to RTC
to CPU1, AHB1, AHB2
to CPU1 FCLK
to CPU1 system timer
to APB1
x1 or
to APB1 TIMx
x2
to APB2
x1 or to APB2 TIMx
x2
to CPU2
to CPU2 FCLK
to CPU2 system timer
to APB3
to RF
to LPTIM1
LSI to LPTIM2
to LPTIM3
LSE
MSv62604V2
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