ST STM32WL55JC Reference Manual page 499

RM0453
The interrupt block diagram is shown in the figure below.
15.3 Interrupt and exception vectors
The CPU1 and CPU2 vector tables are given respectively in
cells indicate the processor exceptions).
Type of
priority
- - -
- -3 Fixed
- -2 Fixed
- -1 Fixed
- 0 Settable MemManager
- 1 Settable
- 2 Settable
- - -
- 3 Settable
- 4 Settable
- - -
Figure 53. Interrupt block diagram
Peripheral
interrupt
Peripheral
interrupt
AIEC
interrupt
interrupt
Peripheral
interrupt
Peripheral
interrupt
Peripheral
interrupt
Table 89. CPU1 vector table
Acronym
- Reserved
Reset Reset
Non maskable interrupt HSE32 CSS, Flash ECC and
NMI
SRAM2 parity
HardFault All classes of fault
Memory manager
BusFault Prefetch fault, memory access fault
UsageFault Undefined instruction or illegal state
- Reserved
SVCall System service can via SWI instruction
Debug Debug monitor
- Reserved
Nested vectored interrupt controller (NVIC)
SYSCFG
C1IMRn
C2IMRn
Description
RM0453 Rev 2
CPU1
NVIC
CPU2
NVIC
Table 89 and Table 90
(1)(2)
MSv60391V1
(shaded
Address
0x0000 0000
0x0000 0004
0x0000 0008
0x0000 000C
0x0000 0010
0x0000 0014
0x0000 0018
0x0000 001C
0x0000 0028
0x0000 002C
0x0000 0030
0x0000 0034
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