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RM0453
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:6 PUPD3[1:0]: Port PH3 pull configuration
Bits 5:0 Reserved, must be kept at reset value.
10.4.27
GPIOH input data register (GPIOH_IDR)
Address offset: 0x1C10
Reset value: 0x0000 000X
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 ID3: Port PH3 input data bit
Bits 2:0 Reserved, must be kept at reset value.
10.4.28
GPIOH output data register (GPIOH_ODR)
Address offset: 0x1C14
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 OD3: Port PH3 output data
This bit can be read and written by software.
Note: For atomic bit set/reset, OD bits can be individually set and/or reset by writing to the
Bits 2:0 Reserved, must be kept at reset value.
These bits are written by software to configure the I/O pull-up or pull-down.
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
This bit is read-only. It contains the input value of the corresponding I/O port.
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
GPIOH_BSRR and GPIOH_BRR registers.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0453 Rev 2
General-purpose I/Os (GPIO)
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
ID3
Res.
r
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
OD3
Res.
rw
17
16
Res.
Res.
1
0
Res.
Res.
17
16
Res.
Res.
1
0
Res.
Res.
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