ST STM32WL55JC Reference Manual page 340

Reset and clock control (RCC)
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:4 C2HPRE[3:0]: HCLK2 prescaler (CPU2)
Caution: Depending on the device voltage range, the software must set correctly these bits to
Bits 3:0 SHDHPRE[3:0]: HCLK3 shared prescaler (AHB3, Flash, SRAM1, and SRAM2)
Caution: Depending on the device voltage range, the software must set correctly these bits to
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These bits are set and cleared by software to control the division factor of the HCLK2 clock
(CPU2). The C2HPREF flag can be checked to know if the programmed C2HPRE prescaler
value is applied. This field is also cleared to all zero (SYSCLK not divided) by hardware when
the system enters Stop mode and HSI16 is selected as wakeup clock.
0001: SYSCLK divided by 3
0010: SYSCLK divided by 5
0101: SYSCLK divided by 6
0110: SYSCLK divided by 10
0111: SYSCLK divided by 32
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512
Others: SYSCLK not divided
ensure that the system frequency does not exceed the maximum allowed frequency
(refer to Section 6.1.4: Dynamic voltage scaling
operation to these bits and before decreasing the voltage range, the C2HPREF bit
must be read to be sure that the new value is taken into account.
These bits are set and cleared by software to control the division factor of the shared HCLK3
clock. (AHB3, Flash, SRAM1 and SRAM2, APB3). The SHDHPREF flag can be checked to
know if the programmed SHDHPRE prescaler value is applied.
0001: SYSCLK divided by 3
0010: SYSCLK divided by 5
0101: SYSCLK divided by 6
0110: SYSCLK divided by 10
0111: SYSCLK divided by 32
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512
Others: SYSCLK not divided
ensure that the system frequency does not exceed the maximum allowed frequency
(refer to Section 6.1.4: Dynamic voltage scaling
operation to these bits and before decreasing the voltage range, the SHDHPRE bit
must be read to be sure that the new value is taken into account.
RM0453 Rev 2
management). After a write
management). After a write
RM0453