Interrupts; Gtzc Tzsc Registers; Gtzc Tzsc Control Register (Gtzc_Tzsc_Cr); Table 8. Tzsc Privileged Mpcwmn Register Memory Allocation - ST STM32WL55JC Reference Manual

Global security controller (GTZC)
3.5.3 GTZC TZSC privileged configuration register
(GTZC_TZSC_PRIVCFGR1)
Address offset: 0x020
Reset value: 0x0000 0000
Privileged write access only.
A bit of this register can be written only by a secure privileged transaction, when the
corresponding bit in GTZC_TZSC_SECCFGR1 register or the Flash user option is set to
secure. If non-secure, the register bit can be written by secure privileged and non-secure
privileged transactions.
Read access is authorized for any type of transaction, secure/non-secure,
privileged/unprivileged.
An illegal access event on a secure access is only generated when all peripheral register
bits in GTZC_TZSC_SECCFGR1 are configured as secure.
When TZSC configuration is locked in GTZC_TZSC_CR.LCK, this register cannot be
modified.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res.
rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 PKAPRIV: Privileged access mode enabled for PKA
Bits 12:5 Reserved, must be kept at reset value.
Bit 4 SUBGHZSPIPRIV: Privileged access mode enabled for sub-GHz SPI
Bit 3 RNGPRIV: Privileged access mode enabled for RNG
Bit 2 AESPRIV: Privileged access mode enabled for AES
Bits 1:0 Reserved, must be kept at reset value.
86/1454
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
0: Unprivileged
1: Privileged
0: Unprivileged
1: Privileged
0: Unprivileged
1: Privileged
0: Unprivileged
1: Privileged
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0453 Rev 2
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res.
rw rw rw
RM0453
17 16
Res. Res.
1 0
Res. Res.