ST STM32WL55JC Reference Manual page 982

Independent watchdog (IWDG)
30.4.5 IWDG window register (IWDG_WINR)
Address offset: 0x10
Reset value: 0x0000 0FFF (reset by Standby mode)
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 WIN[11:0]: Watchdog counter window value
Note: Reading this register returns the reload value from the V
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28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw
These bits are write access protected, see
window value to be compared with the downcounter.
To prevent a reset, the downcounter must be reloaded when its value is lower than the
window register value and greater than 0x0
The WVU bit in the IWDG status register (IWDG_SR)
change the reload value.
may not be valid if a write operation to this register is ongoing. For this reason the value
read from this register is valid only when the WVU bit in the
(IWDG_SR) is reset.
24 23 22
Res. Res. Res.
8 7 6
WIN[11:0]
rw rw rw
Section
RM0453 Rev 2
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
30.3.5, they contain the high limit of the
must be reset in order to be able to
voltage domain. This value
DD
IWDG status register
RM0453
17 16
Res. Res.
1 0
rw rw