ST STM32WL55JC Reference Manual page 71

RM0453
2.6.2 Memory map and register boundary addresses
0xFFFF FFFF
peripherals
0xE000 0000
Peripherals
0x4000 0000
0x2000 0000
0x0000 0000
Reserved
1) Part or all of the memory can be made secure via User Option, granting
only exclusive access to the CPU2.
2) Some peripherals can be made secure, granting only exclusive access to
the CPU2.
3) SRAM2 at these address is only accessible by the CPU1.
Any memory area not allocated to on-chip memories and peripherals is considered
"Reserved".
Figure 3. Memory map
CPU1 CPU2
internal internal
peripherals
SRAM
CODE
0x5801 FFFF
0x5801 0000
0x5800 0000
0x4800 0000
0x4802 0000
0x4001 0000
0x4000 0000
0x2000 FFFF
0x2000 8000
0x2000 0000
0x1FFF 7800
0x1FFF 7400
0x1FFF 7000
0x1000 7FFF
0x1000 0000
0x0803 FFFF
0x0800 0000
0x0003 FFFF
0x0000 0000
RM0453 Rev 2
2)
APB3
2)
AHB3
AHB2
2)
AHB1
APB2
APB1
1)
SRAM2
1)
SRAM1
Reserved
Option Bytes
Reserved
OTP area
System Flash
Reserved
1)3)
SRAM2
Reserved
1)
Flash
Reserved
CPU1 CPU2
Flash, system Flash, system
memory or memory, SRAM1
SRAM1, or SRAM2,
depending on depending on
BOOT BOOT and SBRV
configuration configuration
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