ST STM32WL55JC Reference Manual page 307

RM0453
7.4.5 RCC clock interrupt enable register (RCC_CIER)
Address offset: 0x018
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 LSECSSIE: LSE clock security system interrupt enable
Bits 8:6 Reserved, must be kept at reset value.
Bit 5 PLLRDYIE: PLL ready interrupt enable
Bit 4 HSERDYIE: HSE32 ready interrupt enable
Bit 3 HSIRDYIE: HSI16 ready interrupt enable
28 27 26 25
Res. Res. Res.
12 11 10 9
LSE
Res. Res.
CSSIE
rw
This bit is set and cleared by software to enable/disable interrupt caused by the CSS on
LSE.
0: Clock security interrupt caused by LSE clock failure disabled
1: Clock security interrupt caused by LSE clock failure enabled
This bit is set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
This bit is set and cleared by software to enable/disable interrupt caused by the HSE32
oscillator stabilization.
0: HSE32 ready interrupt disabled
1: HSE32 ready interrupt enabled
This bit is set and cleared by software to enable/disable interrupt caused by the HSI16
oscillator stabilization.
0: HSI16 ready interrupt disabled
1: HSI16 ready interrupt enabled
24 23 22
Res. Res. Res. Res.
8 7 6
Res. Res. Res.
RDYIE
RM0453 Rev 2
Reset and clock control (RCC)
21 20 19 18
Res. Res. Res.
5 4 3 2
PLL HSE HSI MSI
RDYIE RDYIE RDYIE
rw rw rw rw
17 16
Res. Res.
1 0
LSE LSI
RDYIE RDYIE
rw rw
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