Pwr Cpu2 Control Register 3 (Pwr_C2Cr3) - ST STM32WL55JC Reference Manual

Reset and clock control (RCC)
–
–
The functionality in Stop mode (including wakeup) is supported only when the clock is
LSI or LSE.
•
The IWDG clock is always the LSI clock.
The RCC feeds the CPU1 system timer (SysTick) external clock with the AHB clock
(HCLK1) divided by eight. The SysTick can work either with this clock or directly with the
CPU1 clock (HCLK1), configurable in the SysTick control and status register.
FCLK1 acts as CPU1 free-running clock. For more details, refer to the programming manual
STM32 Cortex
The RCC feeds the CPU2 system timer (SysTick) external clock with the AHB clock
(HCLK2) divided by eight. The SysTick can work either with this clock or directly with the
CPU2 clock (HCLK2), configurable in the SysTick control and status register.
FCLK2 acts as CPU2 free-running clock.
280/1454
LSI clock
HSE32 clock divided by 32
®
-M4 MCUs and MPUs programming manual (PM0214).
RM0453 Rev 2
RM0453