ST STM32WL55JC Reference Manual page 874

General-purpose timer (TIM2)
Bit 10 CC2DE: Capture/Compare 2 DMA request enable
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
Bit 8 UDE: Update DMA request enable
Bit 7 Reserved, must be kept at reset value.
Bit 6 TIE: Trigger interrupt enable
Bit 5 Reserved, must be kept at reset value.
Bit 4 CC4IE: Capture/Compare 4 interrupt enable
Bit 3 CC3IE: Capture/Compare 3 interrupt enable
Bit 2 CC2IE: Capture/Compare 2 interrupt enable
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
Bit 0 UIE: Update interrupt enable
26.4.5 TIM2 status register (TIM2_SR)
Address offset: 0x10
Reset value: 0x0000
15 14 13
Res. Res. Res. CC4OF CC3OF CC2OF CC1OF
rc_w0
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CC4OF: Capture/Compare 4 overcapture flag
refer to CC1OF description
Bit 11 CC3OF: Capture/Compare 3 overcapture flag
refer to CC1OF description
Bit 10 CC2OF: Capture/compare 2 overcapture flag
refer to CC1OF description
874/1454
0: CC2 DMA request disabled.
1: CC2 DMA request enabled.
0: CC1 DMA request disabled.
1: CC1 DMA request enabled.
0: Update DMA request disabled.
1: Update DMA request enabled.
0: Trigger interrupt disabled.
1: Trigger interrupt enabled.
0: CC4 interrupt disabled.
1: CC4 interrupt enabled.
0: CC3 interrupt disabled.
1: CC3 interrupt enabled.
0: CC2 interrupt disabled.
1: CC2 interrupt enabled.
0: CC1 interrupt disabled.
1: CC1 interrupt enabled.
0: Update interrupt disabled.
1: Update interrupt enabled.
12 11 10 9
rc_w0 rc_w0 rc_w0
8 7 6
Res. Res. TIF
rc_w0
RM0453 Rev 2
5 4 3 2
Res. CC4IF CC3IF CC2IF
rc_w0 rc_w0 rc_w0
RM0453
1 0
CC1IF UIF
rc_w0 rc_w0