Table 68. Bits Used For The Communication; Figure 37. Ipcc Simplex Channel Mode Transfer Timing - ST STM32WL55JC Reference Manual

RM0453
Bits 21:16 CHnFM: Processor 2 transmit channel n free interrupt mask (n = 6 to 1).
Associated with IPCC_C2TOC1SR.CHnF
1: Transmit channel n free interrupt masked.
0: Transmit channel n free interrupt not masked.
Bits 15:6 Reserved, must be kept at reset value.
Bits 5:0 CHnOM: Processor 2 receive channel n occupied interrupt mask (n = 6 to 1).
Associated with IPCC_C1TOC2SR.CHnF
1: Receive channel n occupied interrupt masked.
0: Receive channel n occupied interrupt not masked.
9.4.7 IPCC processor 2 status set clear register (IPCC_C2SCR)
Address offset: 0x018
Reset value: 0x0000 0000
Reading this register always returns 0x0000 0000.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:16 CHnS: Processor 2 transmit channel n status set (n = 6 to 1).
Associated with IPCC_C2TOC1SR.CHnF
1: Processor 2 transmit channel n status bit set.
0: No action.
Bits 15:6 Reserved, must be kept at reset value.
Bits 5:0 CHnC: Processor 2 receive channel n status clear (n = 6 to 1).
Associated with IPCC_C1TOC2SR.CHnF
1: Processor 2 receive channel n status bit clear.
0: No action.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
Inter-processor communication controller (IPCC)
24 23 22 21
Res. Res. Res. CH6S
rw
8 7 6
Res. Res. Res. CH6C
rw
RM0453 Rev 2
20 19 18
CH5S CH4S CH3S
rw rw rw
5 4 3 2
CH5C CH4C CH3C
rw rw rw
17 16
CH2S CH1S
rw rw
1 0
CH2C CH1C
rw rw
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