Table of Contents
Advertisement
Embedded Flash memory (FLASH)
4.10
FLASH registers
4.10.1
FLASH access control register (FLASH_ACR)
Address offset: 0x000
Reset value: 0x0000 0600
31
30
29
Res.
Res.
Res.
Res.
15
14
13
PES
Res.
Res.
DCRST ICRST
rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 EMPTY: Flash user area empty
Bit 15 PES: CPU1 program/erase suspend request
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 DCRST: CPU1 data cache reset
Bit 11 ICRST: CPU1 instruction cache reset
Bit 10 DCEN: CPU1 data cache enable
Bit 9 ICEN: CPU1 instruction cache enable
128/1454
28
27
26
25
Res.
Res.
Res.
12
11
10
9
DCEN
ICEN
rw
rw
rw
rw
When read, this bit indicates whether the first location of the user Flash is erased or has a
programmed value.
0: Read: user Flash programmed
1: Read: user Flash empty
0: Flash program and erase operations granted
1: Any new Flash program and erase operation is suspended until this bit and the same bit in
FLASH_C2ACR are cleared. The PESD bit in FLASH_SR and FLASH_C2SR areset when
at least one PES bit in FLASH_ACR or FLASH_C2ACR is set.
0: CPU1 data cache not reset
1: CPU1 data cache reset
This bit can be written only when the data cache is disabled.
0: CPU1 instruction cache not reset
1: CPU1 instruction cache reset
This bit can be written only when the instruction cache is disabled.
0: CPU1 data cache disabled
1: CPU1 data cache enabled
0: CPU1 instruction cache disabled
1: CPU1 instruction cache enabled
24
23
22
Res.
Res.
Res.
8
7
6
PRFTEN
Res.
Res.
rw
RM0453 Rev 2
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
rw
RM0453
17
16
Res.
EMPTY
rw
1
0
LATENCY[2:0]
rw
rw
Advertisement
Chapters
Table of Contents
Need help?
Do you have a question about the STM32WL55JC and is the answer not in the manual?