ST STM32WL55JC Reference Manual page 813

RM0453
Bits 31:0 DMAB[31:0]: DMA register for burst accesses
25.4.23 TIM1 option register 1 (TIM1_OR1)
Address offset: 0x50
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:5 Reserved, must be kept at reset value.
Bit 4 TI1_RMP: Input Capture 1 remap
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 TIM1_ETR_ADC_RMP[1:0]: TIM1_ETR_ADC remapping capability
Note: ADC AWDx sources are 'ORed' with the TIM1_ETR input signals. When ADC AWDx is
25.4.24 TIM1 capture/compare mode register 3
(TIM1_CCMR3)
Address offset: 0x54
Reset value: 0x0000 0000
The channels 5 and 6 can only be configured in output.
Output compare mode:
A read or write operation to the DMAR register accesses the register located at the address
(TIMx_CR1 address) + (DBA + DMA index) x 4
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA
transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
0: TIM1 input capture 1 is connected to I/O
1: TIM1 input capture 1 is connected to COMP1 output
00: TIM1_ETR is not connected to ADC AWDx (must be selected when the ETR comes from
the ETR input pin)
01: TIM1_ETR is connected to ADC AWD1
10: TIM1_ETR is connected to ADC AWD2
11: TIM1_ETR is connected to ADC AWD3
used, it is necessary to make sure that the corresponding TIM1_ETR input pin is not
enabled in the alternate function controller.
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0453 Rev 2
Advanced-control timer (TIM1)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
TI1_
Res. Res. Res.
RMP
rw
17 16
Res. Res.
1 0
TIM1_ETR_
ADC_RMP[1:0]
rw rw
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