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General-purpose I/Os (GPIO)
10.4.32
GPIOH bit reset register (GPIOH_BRR)
Address offset: 0x1C28
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 BR3: Port PH3 reset output data bit [3] in GPIOH_ODR
Bits 2:0 Reserved, must be kept at reset value.
10.4.33
GPIOA register map
The following table gives the GPIOA register map and reset values.
Offset Register name
GPIOA_MODER
0x0000
Reset value
GPIOA_OTYPER
0x0004
Reset value
GPIOA_OSPEEDR
0x0008
Reset value
GPIOA_PUPDR
0x000C
Reset value
GPIOA_IDR
0x0010
Reset value
GPIOA_ODR
0x0014
Reset value
422/1454
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
This bit is read clear-write 1. A read to this bit returns the value 0.
0: No action on the corresponding GPIOH_ODR.OD3
1: Resets the corresponding GPIOH_ODR.OD3.
Table 71. GPIOA register map and reset values
1
0
1
0
1
0
1
1
0
0
0
0
1
1
0
0
0
1
1
0
0
1
0
0
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
0
RM0453 Rev 2
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
BR3
Res.
rc_w1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
RM0453
17
16
Res.
Res.
1
0
Res.
Res.
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
x
x
0
0
0
0
0
0
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