Table 62. Low-Power Debug Configurations - ST STM32WL55JC Reference Manual

Reset and clock control (RCC)
Bits 14:8 PLLN[6:0]: Main PLL multiplication factor for VCO
Caution: The software must set correctly these bits to assure that the VCO output frequency
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 PLLM[2:0]: Division factor for the main PLL input clock
Caution: The software must set these bits correctly to ensure that the VCO input frequency
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 PLLSRC[1:0]: Main PLL entry clock source
306/1454
These bits are set and cleared by software to control the multiplication factor of the VCO.
They can be written only when the PLL is disabled.
VCO output frequency = VCO input frequency x PLLN with 6< PLLN < 127
0000000: Reserved must not be used.
...
0000101: Reserved (must not be used)
0000110: PLLN = 6
0000111: PLLN = 7
...
1010101: PLLN = 85
1010110: PLLN = 86
...
1111111: PLLN = 127
is between 96 and 344 MHz.
These bits are set and cleared by software to divide the PLL input clock before the VCO.
They can be written only when the PLL is disabled.
VCO input frequency = PLL input clock frequency / PLLM with 1 < PLLM < 8
000: PLLM = 1
001: PLLM = 2
010: PLLM = 3
011: PLLM = 4
100: PLLM = 5
101: PLLM = 6
110: PLLM = 7
111: PLLM = 8
ranges from 2.66 to 16 MHz.
These bits are set and cleared by software to select PLL clock source. They can be written
only when PLL is disabled. In order to save power, when no PLL is used, the value of
PLLSRC must be 0.
00: No clock sent to PLL
01: MSI clock selected as PLL clock entry
10: HSI16 clock selected as PLL clock entry
11: HSE32 clock selected as PLL clock entry
RM0453 Rev 2
RM0453