Pwr Status Clear Register (Pwr_Scr) - ST STM32WL55JC Reference Manual

RM0453
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 NSS: sub-GHz SPI NSS control
This bit is set and cleared by software and is used to control the sub-GHz SPI NSS level from
software.
0: sub-GHz SPI NSS signal at level low
1: sub-GHz SPI NSS signal is at level high
Bits 14:0 Reserved, must be kept at reset value.
6.6.22 PWR RSS command register (PWR_RSSCMDR)
This register is only reset by a power-on reset (not reset on NRST and exit from Standby).
Address offset: 0x098
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 RSSCMD[7:0]: RSS command
Define a command to be executed by the RSS.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
24 23 22
Res. Res. Res.
8 7 6
Res.
rw rw
RM0453 Rev 2
Power control (PWR)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
RSSCMD[7:0]
rw rw rw rw
17 16
Res. Res.
1 0
rw rw
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