Gtzc Tzic Interrupt Status Clear Register 1 (Gtzc_Tzic_Icr1) - ST STM32WL55JC Reference Manual

RM0453
4 Embedded Flash memory (FLASH)
4.1 FLASH introduction
The Flash memory interface manages the CPU1 AHB ICode and DCode accesses and the
CPU2 AHB access to the Flash memory. It implements the access arbitration between the
two CPUs, the erase and program Flash memory operations, the security mechanisms, and
the read and write protection.
The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines.
4.2 FLASH main features
•
Up to 256 Kbytes of Flash memory single bank architecture
•
Memory organization: 1 bank
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–
•
72-bit wide data read (64 bits plus 8 ECC bits)
•
72-bit wide data write (64 bits plus 8 ECC bits)
•
Page erase (2 Kbytes) and mass erase
Flash memory interface features:
•
Flash memory read operations
• Flash memory program/erase operations
•
Readout protection activated by option (RDP)
• 2 write protection areas selected by option (WRP)
•
2 proprietary code readout protection area selected by option (PCROP)
• CPU2 security area
•
CPU2
• Flash empty check
•
Program and erase suspension feature
• Prefetch on CPU1 ICODE and CPU2 S-bus
•
CPU1 instruction cache: 32 cache lines of 4 x 64 bits on ICode (1-Kbyte RAM)
• CPU1 data cache: 8 cache lines of 4 x 64 bits on DCode (256-byte RAM)
•
CPU2 instruction cache: 4 cache lines of 1 x 64 bits on S-bus (32-byte RAM)
•
Error code correction (ECC): 8 bits for 64-bit
•
Option byte loader
4.3 FLASH functional description
4.3.1 Flash memory organization
The Flash memory is organized as 72-bit wide memory cells (64 bits plus 8 ECC bits) that
can be used for storing both code and data constants.
main memory: up to 256 Kbytes
page size: 2 Kbytes
area
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RM0453 Rev 2
Embedded Flash memory (FLASH)
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