ST STM32WL55JC Reference Manual page 811

RM0453
Bit 10 OSSI: Off-state selection for Idle mode
This bit is used when MOE=0 due to a break event or by a software write, on channels
configured as outputs.
See OC/OCN enable description for more details
enable register
0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which
1: When inactive, OC/OCN outputs are first forced with their inactive level then forced to their
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
Bits 9:8 LOCK[1:0]: Lock configuration
These bits offer a write protection against software errors.
00: LOCK OFF - No bit is write protected.
01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in
Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
Bits 7:0 DTG[7:0]: Dead-time generator setup
This bit-field defines the duration of the dead-time inserted between the complementary
outputs. DT correspond to this duration.
DTG[7:5] = 0xx => DT = DTG[7:0] x t
DTG[7:5] = 10x => DT = (64 + DTG[5:0]) x t
DTG[7:5] = 110 => DT = (32 + DTG[4:0]) x t
DTG[7:5] = 111 => DT = (32 + DTG[4:0]) x t
Example if t
0 to 15875 ns by 125 ns steps,
16 μs to 31750 ns by 250 ns steps,
32 μs to 63 μs by 1 μs steps,
64 μs to 126 μs by 2 μs steps
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
25.4.21 TIM1 DMA control register (TIM1_DCR)
Address offset: 0x48
Reset value: 0x0000
15 14 13
Res. Res. Res.
Bits 15:13 Reserved, must be kept at reset value.
(TIM1_CCER)).
is taken over by the GPIO logic and which imposes a Hi-Z state).
idle level after the deadtime. The timer maintains its control over the output.
bits in TIMx_BDTR register).
register and BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0],
AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits in TIMx_BDTR register can no longer
be written.
register, as long as the related channel is configured in output through the CCxS bits) as
well as OSSR and OSSI bits can no longer be written.
TIMx_CCMRx registers, as long as the related channel is configured in output through
the CCxS bits) can no longer be written.
has been written, their content is frozen until the next reset.
= 125 ns (8 MHz), dead-time possible values are:
DTS
(LOCK bits in TIMx_BDTR register).
12 11 10 9
DBL[4:0]
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(Section 25.4.11: TIM1 capture/compare
with t
DTG DTG
with t
DTG
with t
DTG
with t
DTG
8 7 6
Res. Res.
rw
RM0453 Rev 2
Advanced-control timer (TIM1)
= t .
DTS
= 2 x t .
DTG DTS
= 8 x t .
DTG DTS
= 16 x t .
DTG DTS
5 4 3 2
Res. DBA[4:0]
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1 0
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