ST STM32WL55JC Reference Manual page 96

Global security controller (GTZC)
Bit 4 SUBGHZSPICF: Illegal access event interrupt status flag clear bit for sub-GHz SPI
Bit 3 RNGCF: Illegal access event interrupt status flag clear bit for RNG
Bit 2 AESCF: Illegal access event interrupt status flag clear bit for AES
Bit 1 TZSCCF: Illegal access event interrupt status flag clear bit for GTZC TZSC
Bit 0 TZICCF: Illegal access event interrupt status flag clear bit for GTZC TZIC
3.6.4 GTZC TZIC register map
Register
Offset
GTZC_TZIC_IER1
0x000
Reset value
0x004
to Reserved
0x00C
GTZC_TZIC_MISR1
0x010
Reset value
0x014
to Reserved
0x01C
GTZC_TZIC_ICR1
0x020
Reset value
Refer to
96/1454
0: No action
1: Clear status flag
0: No action
1: Clear status flag
0: No action
1: Clear status flag
0: No action
1: Clear status flag
0: No action
1: Clear status flag
Table 10. TZIC register map and reset values
Section 2.6 for the register boundary addresses.
Reserved
Reserved
RM0453 Rev 2
x x x x x x x x x
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
RM0453
x x x x x
0 0 0 0 0
0 0 0 0 0