Figure 229. Control Circuit In Trigger Mode - ST STM32WL55JC Reference Manual

General-purpose timer (TIM2)
Figure 232. Master/slave connection example with 1 channel only timers
Clock
Prescaler Counter
Compare 1
Note: The timers with one channel only (see
the OC1 output signal can be used to trigger some other timers (including timers described
in other sections of this document). Check the "TIMx internal trigger connection" table of any
TIMx_SMCR register on the device to identify which timers can be targeted as slave.
The OC1 signal pulse width must be programmed to be at least 2 clock cycles of the
destination timer, to make sure the slave timer will detect the trigger.
For instance, if the destination's timer CK_INT clock is 4 times slower than the source timer,
the OC1 pulse width must be 8 clock cycles.
Using one timer as prescaler for another timer
For example, TIM1 can be configured to act as a prescaler for TIM2. Refer to
do this:
1. Configure TIM1 in master mode so that it outputs a periodic trigger signal on each
update event UEV. If MMS=010 is written in the TIM1_CR2 register, a rising edge is
output on TRGO each time an update event is generated.
2. To connect the TRGO output of TIM1 to TIM2, TIM2 must be configured in slave mode
using ITR0 as internal trigger. This is selected through the TS bits in the TIM2_SMCR
register (writing TS=00000).
3. Then the slave mode controller must be put in external clock mode 1 (write SMS=111 in
the TIM2_SMCR register). This causes TIM2 to be clocked by the rising edge of the
periodic TIM1 trigger signal (which correspond to the TIM1 counter overflow).
4. Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1
register).
Note: If OCx is selected on TIM1 as the trigger output (MMS=1xx), its rising edge is used to clock
the counter of TIM2.
Using one timer to enable another timer
In this example, we control the enable of TIM2 with the output compare 1 of Timer 1. Refer
to Figure 231
of TIM1 is high. Both counter clock frequencies are divided by 3 by the prescaler compared
to CK_INT (f
862/1454
TIM_mstr
Output
tim_oc1
control
TIM_CH1
for connections. TIM2 counts on the divided internal clock only when OC1REF
= f /3).
CK_CNT CK_INT
TS
SMS
Slave
tim_itr
mode
control
Input
trigger
selection
Figure 232) do not feature a master mode. However,
RM0453 Rev 2
TIM_slv
CK_PSC
Prescaler
Figure
RM0453
Counter
MSv65225V1
231. To