Table 104. Configuring The Trigger Polarity; Figure 66. Stopping An Ongoing Conversion - ST STM32WL55JC Reference Manual

Analog-to-digital converter (ADC)
RES[1:0]
bits
12
10
8
6
18.4.3 End of conversion, end of sampling phase (EOC, EOSMP flags)
The ADC indicates each end of conversion (EOC) event.
The ADC sets the EOC flag in the ADC_ISR register as soon as a new conversion data
result is available in the ADC_DR register. An interrupt can be generated if the EOCIE bit is
set in the ADC_IER register. The EOC flag is cleared by software either by writing 1 to it, or
by reading the ADC_DR register.
The ADC also indicates the end of sampling phase by setting the EOSMP flag in the
ADC_ISR register. The EOSMP flag is cleared by software by writing1 to it. An interrupt can
be generated if the EOSMPIE bit is set in the ADC_IER register.
The aim of this interrupt is to allow the processing to be synchronized with the conversions.
Typically, an analog multiplexer can be accessed in hidden time during the conversion
phase, so that the multiplexer is positioned when the next sampling starts.
Note: As there is only a very short time left between the end of the sampling and the end of the
conversion, it is recommenced to use polling or a WFE instruction rather than an interrupt
and a WFI instruction.
18.4.4 End of conversion sequence (EOS flag)
The ADC notifies the application of each end of sequence (EOS) event.
The ADC sets the EOS flag in the ADC_ISR register as soon as the last data result of a
conversion sequence is available in the ADC_DR register. An interrupt can be generated if
the EOSIE bit is set in the ADC_IER register. The EOS flag is cleared by software by writing
1 to it.
548/1454
Table 105. t
SAR
t
SAR
t (ns) at
SAR
(ADC clock
f = 35 MHz
ADC
cycles)
12.5 357
10.5 300
8.5 243
6.5 186
RM0453 Rev 2
timings depending on resolution
t
SMPL (min)
(ADC clock cycles)
(ADC clock
cycles)
(with min. t
1.5
1.5
1.5
1.5
RM0453
t
CONV
t (ns) at
CONV
f = 35 MHz
ADC
)
SMPL
14 400
12 343
10 286
8 229