Gtzc Tzic Register Map; Table 10. Tzic Register Map And Reset Values - ST STM32WL55JC Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Embedded Flash memory (FLASH)
The Flash memory is organized as follows:
A main memory block containing 128 pages of 2 Kbytes, each page with eight rows of
256 bytes.
An information block containing:
The memory organization is based on a main area and an information block as shown in the
table below.
Area
Main memory
Information block
4.3.2
Empty check
During the OBL phase, after loading all options, the Flash memory interface checks whether
the first location of the main memory is programmed. The result of this check, in conjunction
with the BOOT0 and BOOT1 information, is used to determine where the system has to
98/1454
System memory from which the CPU1 boots in system memory boot mode
This area is reserved and contains the bootloader used to reprogram the Flash
memory through one of the following interfaces: USART1, USART2, I2C1, I2C2,
I2C3, SPI1, SPI2S2. It is programmed by STMicroelectronics when the device is
manufactured and protected against spurious write/erase operations. For further
details, refer to the application note STM32 microcontroller system memory boot
mode (AN2606).
System memory from which the CPU2 boots in System memory boot mode
This area is reserved and contains the SFI/RSS firmware used to authenticate and
install the firmware in Flash memory through one of the following interfaces:
USART1, USART2, I2C1, I2C2, I2C3, SPI1, SPI2S2. It is programmed by
STMicroelectronics when the device is manufactured, and protected against
spurious write/erase operations.
1-Kbyte (128 double-word) OTP (one-time programmable) for user data
The OTP data cannot be erased and can be written only once. If only one bit is at
0, the entire double-word (64 bits) cannot be written anymore, even with the value
0x0000 0000 0000 0000. The OTP area cannot be read when RDP level is 1 and
boot source is not Flash user area.
Option bytes for user configuration
Table 11. Flash memory - Single bank organization
0x0800 0000 - 0x0800 07FF
0x0800 8000 - 0x0800 0FFF
0x0800 1000 - 0x0800 17FF
0x0800 1800 - 0x0800 1FFF
0x083 F000 - 0x0803 F7FF
0x083 F800 - 0x0803 FFFF
0x1FFF 0000 - 0x1FFF 6FFF
0x1FFF 7000 - 0x1FFF 73FF
0x1FFF 7800 - 0x1FFF 7FFF
Addresses
...
RM0453 Rev 2
Size (Kbytes)
2
2
2
2
...
2
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2
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28
System memory
1
OTP area
2
Option bytes
RM0453
Name
Page 0
Page 1
Page 2
Page 3
...

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