ST STM32WL55JC Reference Manual page 309

RM0453
Bit 4 HSERDYF: HSE32 ready interrupt flag
Bit 3 HSIRDYF: HSI16 ready interrupt flag
Bit 2 MSIRDYF: MSI ready interrupt flag
Bit 1 LSERDYF: LSE ready interrupt flag
Bit 0 LSIRDYF: LSI ready interrupt flag
7.4.7 RCC clock interrupt clear register (RCC_CICR)
Address offset: 0x020
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
This bit is set by hardware when the HSE32 clock becomes stable and HSERDYDIE is set.
It is cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the HSE32 oscillator
1: Clock ready interrupt caused by the HSE32 oscillator
This bit is set by hardware when the HSI16 clock becomes stable and HSIRDYDIE is set in
a response to setting the HSION in the RCC_CR register. When HSION is not set but the
HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and
no interrupt is generated. This bit is cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the HSI16 oscillator
1: Clock ready interrupt caused by the HSI16 oscillator
This bit is set by hardware when the MSI clock becomes stable and MSIRDYDIE is set. It is
cleared by software setting the MSIRDYC bit.
0: No clock ready interrupt caused by the MSI oscillator
1: Clock ready interrupt caused by the MSI oscillator
This bit is set by hardware when the LSE clock becomes stable and LSERDYDIE is set. It is
cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
This bit is set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. It is
cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator
28 27 26 25
Res. Res. Res.
12 11 10 9
LSE
Res. Res.
CSSC
w
24 23 22
Res. Res. Res. Res.
8 7 6
CSSC Res. Res.
RDYC
w
RM0453 Rev 2
Reset and clock control (RCC)
21 20 19 18
Res. Res. Res.
5 4 3 2
PLL HSE HSI MSI
RDYC RDYC RDYC
w w w w
17 16
Res. Res.
1 0
LSE LSI
RDYC RDYC
w w
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