ST STM32WL55JC Reference Manual page 923

RM0453
Bit 1 UDIS: Update disable
Bit 0 CEN: Counter enable
Note: External clock and gated mode can work only if the CEN bit has been previously set by
27.4.2 TIMx control register 2 (TIMx_CR2)(x = 16 to 17)
Address offset: 0x04
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 OIS1N: Output Idle state 1 (OC1N output)
0: OC1N=0 after a dead-time when MOE=0
1: OC1N=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
Bit 8 OIS1: Output Idle state 1 (OC1 output)
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 CCDS: Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bit 2 CCUS: Capture/compare control update selection
0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
Note: This bit acts only on channels that have a complementary output.
Bit 1 Reserved, must be kept at reset value.
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit
is set or if a hardware reset is received from the slave mode controller.
0: Counter disabled
1: Counter enabled
software. However trigger mode can set the CEN bit automatically by hardware.
12 11 10 9
Res. Res. OIS1N
rw
(LOCK bits in TIMx_BDTR register).
(LOCK bits in TIMx_BDTR register).
the COMG bit only.
the COMG bit or when an rising edge occurs on TRGI.
General-purpose timers (TIM16/TIM17)
8 7 6
OIS1 Res. Res.
rw
RM0453 Rev 2
5 4 3 2
Res. Res. CCDS CCUS
rw rw
1 0
Res. CCPC
rw
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