Figure 236. Triggering Tim2 With Enable Of Tim1 - ST STM32WL55JC Reference Manual

RM0453
26.4 TIM2 registers
In this section, "TIMx" should be understood as "TIM2" since there is only one instance of
this type of timer for the products to which this reference manual applies.
Refer to
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
26.4.1 TIM2 control register 1 (TIM2_CR1)
Address offset: 0x00
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 UIFREMAP: UIF status bit remapping
Bit 10 Reserved, must be kept at reset value.
Bits 9:8 CKD[1:0]: Clock division
Bit 7 ARPE: Auto-reload preload enable
Bits 6:5 CMS[1:0]: Center-aligned mode selection
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as
Section 1.2 for a list of abbreviations used in register descriptions.
12 11 10 9
UIFRE
Res. CKD[1:0]
MAP
rw rw
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (ETR, TIx),
00: t = t
DTS CK_INT
01: t = 2 × t
DTS CK_INT
10: t = 4 × t
DTS CK_INT
11: Reserved
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
both when the counter is counting up or down.
the counter is enabled (CEN=1)
8 7 6
ARPE CMS[1:0]
rw rw rw
RM0453 Rev 2
General-purpose timer (TIM2)
5 4 3 2
DIR OPM URS
rw rw rw rw
1 0
UDIS CEN
rw rw
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